The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs).
With recent advancement in semiconductor device manufacturing, and in particular with regard to FinFETs, epitaxially formed source/drain regions are increasingly becoming preferred to provide low resistance contacts to the FinFETs and other devices. Typically, a FinFET device will include one or more fins having a source epitaxy formed thereon separated, by a gate structure, from one or more fins having a drain epitaxy thereon. The gate structure of one FinFET device is typically separated from the gate structure of an adjacent FinFET device by a portion of an underlying substrate. However, as device size continues to shrink, problems may arise with shorting between small pitch structures.